The latest generations of EPROM memory devices show an improvement in various device parameters included in specifications by manufacturers. The transistor density of the devices and their speed have increased, while power consumption both during the active phase and during the standby phase has decreased. However, some of these parameters conflict with one another. In particular, speed is negatively affected by increased transistor density. That is, increased transistor density entails larger resistors and capacitors distributed among the rows and columns of the cell matrix of the device, which in turn increases the RC time constants. Increased RC time constants result in slower device speeds. Thus, a device may have increased transistor density, but at the price of slower device speeds.
There are two particular factors which limit the speed of the device: one, the delay related to the RC time constant of the row in the cell matrix (resistance R of the polysilicon conductor, capacitance C of the gates of the cells connected in parallel to the row); and, two, the delay related to the capacitance of the column in the cell matrix (i.e., of the drain junctions of the connected cells). The delay resulting from the row time constant RC can be decreased through technological solutions which reduce the resistivity of the conductor. The delay due to the capacitance of the column of cells in the matrix, however, has yet to be coped with satisfactorily.